Conventionally, a storage controller, which is connected between a host system, such as a host computer, and a storage apparatus such as a hard disk drive and which controls data I/O between the host system and storage apparatus, is known.
Upon receiving a read/write request from the host system, the storage controller temporarily stores read/write target data (hereinbelow called ‘user data’) in the memory based on the received read/write request. In addition, the storage controller also stores ‘control information’ for controlling operations in the apparatus/system.
The memory which the storage controller comprises typically uses both an involatile memory such as flash memory, which is capable of retaining data even when the power source of the storage controller is cut and volatile memory such as DRAM (Dynamic Random Access Memory), which is not capable of retaining data when the power source of the storage controller is cut. Furthermore, typically, the involatile memory is used as cache memory and the volatile memory is used as local memory. Furthermore, each of the parts in the cache memory and local memory and the storage controller are connected by parallel buses.
As mentioned above, one of the parallel buses is connected to a cache memory and local memory, while the other parallel bus is connected to a data transfer control unit such as an LSI (Large Scale Integration) or ASIC (Application Specific Integrated Circuit) and to a central processing unit such as CPU (Central Processing Unit). Furthermore, the data transfer control unit and central processing unit input user data and control information and so on via a parallel bus.
Here, since a transfer system such as a parallel bus is a system which transfers data in parallel, the connector requires a plurality of pins. Hence, if the data transfer speed is to be improved by increasing the memory bandwidth, a large number of pins are required and there is then the problem of the costs involved in preparing the applicable LSI or ASIC and CPU and the like.
Therefore, PTL1 discloses a technology according to which, when part of the data to be stored in the cache memory is stored in the local memory, part of the local memory storage area is used as cache memory. Technology for using the local memory as involatile memory by means of a battery backup (BBU: Battery Back Up) function is also disclosed.
By using part of the local memory storage area as cache memory, the memory bandwidth which can be used as cache memory can be increased and the data transfer speed can be improved. Furthermore, the local memory is, as mentioned above, typically a volatile memory and is incapable of retaining data when the power source is cut, however, by rendering the local memory involatile memory using the BBU function, the reliability of the data stored in the local memory can be ensured.